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Waferscale Network Switches

Published in ISCA-51st (IEEE Micro Top Pick 2025), 2024

This paper proposes using chiplet-based waferscale integration technology to build waferscale network switches that have 32x higher radix than state-of-the-art switch ASIC.

Recommended citation: S. Chen, S. Pal and R. Kumar, "Waferscale Network Switches," 2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA), Buenos Aires, Argentina, 2024, pp. 215-229, doi: 10.1109/ISCA59077.2024.00025. https://davidchen.page/files/Waferscale-Network-Switches.pdf

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teaching

ECE 408 Applied Parallel Programming

Undergraduate course, UIUC, 2023

I’m a teaching assistant for ECE 408 Applied Parallel Programming. I designed and modified the final project for the course where the students need to implement a CNN kernel with CUDA, profile the execution and optimize the performance. I also assisted in crafting problems for the midterms and grading.