Waferscale Silicon Photonics Systems: A Cost-Benefit Analysis and Optimization

Waveguide network connecting transceiver banks across tiles, with Mach-Zehnder switches enabling reconfigurable logical topologies — Figure 5: Transceiver banks and a generic waveguide network, with Mach-Zehnder switches supporting reconfigurable connections. From the paper, p. 3.

Authors: Robert Bao, Zongrui Cai, Shuangliang Chen, Ajay Joshi, Darius Bunandar, and Rakesh Kumar. Robert Bao and Zongrui Cai contributed equally.

Abstract

Silicon photonics holds considerable promise for reducing long reach communication overheads in future computing systems. Similarly, waferscale integration promises dramatic improvements in performance and energy efficiency for scale out systems, but suffers from the long reach limitations of electrical interconnects. No prior work has looked at the performance benefits of silicon photonics over electrical interconnects to address the long reach challenges of waferscale integration, or at the overheads of silicon photonics for such systems across multiple implementations. In this work, we study a tile-based silicon photonics waferscale system for different implementations of waveguide networks and topologies, and across multiple applications and number of tiles. We find that the performance benefits of using silicon photonics instead of electrical interconnects at waferscale are highly application-dependent - benefits primarily come from reduced communication latency. The power and area overheads of implementation are high, especially for high connectivity topologies and when reconfigurability is considered. Some implementations are infeasible - the microring resonator maximum power limits are exceeded for these implementations. Custom waveguide networks address the problem and limit the overheads when supporting high connectivity topologies and reconfigurability. Overall, this is the first paper to analyze the performance benefits of silicon photonics vs electrical interconnects at waferscale and optimize the implementation overheads of waferscale silicon photonics systems.