Waferscale Network Switches
Published in ISCA-51st, 2024
This paper proposes using chiplet-based waferscale integration technology to build waferscale network switches that have 32x higher radix than state-of-the-art switch ASIC.
Recommended citation: S. Chen, S. Pal and R. Kumar, "Waferscale Network Switches," 2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture (ISCA), Buenos Aires, Argentina, 2024, pp. 215-229, doi: 10.1109/ISCA59077.2024.00025. https://davidchen.page/files/Waferscale-Network-Switches.pdf